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1 of 21 022103 features unique 1-wire ? interface requires only one port pin for communication each device has a unique 64-bit serial code stored in an onboard rom multidrop capability simplifies distributed temperature sensing applications requires no external components can be powered from data line. power supply range is 3.0v to 5.5v measures temperatures from ?55c to +125c (?67f to +257f) 0.5 c accuracy from ?10c to +85c 9-bit thermometer resolution converts temperature in 750ms (max.) user-definable nonvolatile (nv) alarm settings alarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alarm condition) applications include thermostatic controls, industrial systems, consumer products, thermometers, or any thermally sensitive system pin assignment pin description gnd - ground dq - data in/out v dd - power supply voltage nc - no connect description the DS18S20 digital thermometer pr ovides 9-bit centigrade temper ature measurements and has an alarm function with nonvolatile us er-programmable upper and lowe r trigger points. the DS18S20 communicates over a 1-wire bus th at by definition requires only one data line (and ground) for communication with a central microprocessor. it ha s an operating temperature range of ?55c to +125c and is accurate to 0.5 c over the range of ?10c to +85c. in addition, the DS18S20 can derive power directly from the data line (?parasite power?), e liminating the need for an external power supply. each DS18S20 has a unique 64-bit serial code, which allows multiple DS18S20s to function on the same 1-wire bus; thus, it is simple to use one microprocessor to contro l many DS18S20s distributed over a large area. applications that can benefit from th is feature include hvac environmental controls, temperature monitoring systems inside buildings, e quipment or machinery, and process monitoring and control systems. DS18S20 high-precision 1-wire digital thermomete r www. maxim - ic .com 8-pin 150mil so (DS18S20z) to-92 ( DS18S20 ) 1 ( bottom view ) 23 dallas ds1820 1 gnd dq v dd 23 n c nc nc nc gnd dq v dd n c 6 8 7 5 3 1 2 4 ds1820 1-wire is a registered trademark of dallas semiconductor.
DS18S20 2 of 21 detailed pin descriptions table 1 8-pin soic* to-92 symbol description 5 1 gnd ground. 42dq data input/output pin. open-drain 1-wire interface pin. also provides power to the device when used in parasite power mode (see ?parasite power? section.) 33v dd optional v dd pin. v dd must be grounded for operation in parasite power mode. *all pins not specified in this table are ?no connect? pins. overview figure 1 shows a block diagram of the DS18S20, and pin descriptions are given in table 1. the 64-bit rom stores the device?s unique serial code. the sc ratchpad memory contains the 2-byte temperature register that stores the digital output from the te mperature sensor. in add ition, the scratchpad provides access to the 1-byte upper and lower alarm trigger registers (t h and t l ). the t h and t l registers are nonvolatile (eeprom), so they will retain data when the device is powered down. the DS18S20 uses dallas? exclusive 1-wire bus protocol that imple ments bus communication using one control signal. the control line requires a weak pullup re sistor since all devices are linked to the bus via a 3-state or open-drain port (the dq pin in the case of the DS18S20). in this bus system, the microprocessor (the master device) identifies a nd addresses devices on the bus usin g each device?s unique 64-bit code. because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. the 1-wire bus protocol, including detailed explanations of the commands and ?time slots,? is covered in the 1-wire bus system section of this datasheet. another feature of the DS18S20 is the ability to ope rate without an external power supply. power is instead supplied through the 1-wire pullup resistor via the dq pin when the bus is high. the high bus signal also charges an internal capacitor (c pp ), which then supplies power to the device when the bus is low. this method of deriving power from the 1-wire bus is referred to as ?parasite power.? as an alternative, the DS18S20 may also be powered by an external supply on v dd . DS18S20 block diagram figure 1 v pu 4.7k power supply sense 64-bit rom and 1-wire port d q v dd internal v dd c pp parasite power circuit memory control logic scratchpad 8-bit crc generator temperature sensor alarm high trigger (t h ) register (eeprom) alarm low trigger (t l ) register (eeprom) gnd DS18S20
DS18S20 3 of 21 operation ? measuring temperature the core functionality of the DS18S20 is its direct-t o-digital temperature sens or. the temperature sensor output has 9-bit resolution, which corresponds to 0.5 c steps. the DS18S20 powers-up in a low-power idle state; to initiate a temperature measurement a nd a-to-d conversion, the master must issue a convert t [44h] command. following the conversion, the resu lting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18S20 returns to its idle state. if the DS18S20 is powered by an external supply, the ma ster can issue ?read-time slots? (see the 1-wire bus system section) after the convert t command and the DS18S20 will respond by transmitting 0 while the temperature conversion is in progress and 1 when th e conversion is done. if the DS18S20 is powered with parasite power, this notification t echnique cannot be used since the bus must be pulled high by a strong pullup during the entire temperature conversion. the bus requirements for parasite power are explained in detail in the powering the DS18S20 section of this datasheet. the DS18S20 output data is calibrated in degrees ce ntigrade; for fahrenheit a pplications, a lookup table or conversion routine must be use d. the temperature data is stored as a 16-bit sign-extended two?s complement number in the temperature register (see figure 2). the sign bits (s) indicate if the temperature is positive or negative: for positive numbe rs s = 0 and for negative numbers s = 1. table 2 gives examples of digital output data and the corresponding temperature reading. resolutions greater than 9 bits can be calculated using the data from the temperature, count remain and count per c registers in the scratchpad. note that the count per c register is hard-wired to 16 (10h). after reading the scratchpad, the temp_ read value is obtained by truncating the 0.5 c bit (bit 0) from the temperature data (see figure 2). the extended resolution temperature can then be calculated using the following equation: c per count remain count c per count read temp e temperatur _ _ _ _ _ 25 . 0 _ temperature register format figure 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte ssssssss temperature/data relationship table 2 temperature digital output (binary) digital output (hex) +85.0c* 0000 0000 1010 1010 00aah +25.0c 0000 0000 0011 0010 0032h +0.5c 0000 0000 0000 0001 0001h 0c 0000 0000 0000 0000 0000h -0.5c 1111 1111 1111 1111 ffffh -25.0c 1111 1111 1100 1110 ffceh -55.0c 1111 1111 1001 0010 ff92h *the power-on reset value of the temperature register is +85c
DS18S20 4 of 21 operation ? alarm signaling after the DS18S20 performs a temperature conversion, the temperature value is compared to the user- defined two?s complement alarm trigge r values stored in the 1-byte t h and t l registers (see figure 3). the sign bit (s) indicates if the value is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. the t h and t l registers are nonvolatile (eeprom) so they will retain data when the device is powered down. t h and t l can be accessed through bytes 2 and 3 of the scratchpad as explained in the memory section of this datasheet. t h and t l register format figure 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s2 6 2 5 2 5 2 5 2 2 2 1 2 0 only bits 8 through 1 of the temperature register are used in the t h and t l comparison since t h and t l are 8-bit registers. if the measured temperature is lower than or equal to t l or higher than t h , an alarm condition exists and an alarm flag is set inside th e DS18S20. this flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion. the master device can check the alarm flag status of all DS18S20s on the bus by issuing an alarm search [ech] command. any DS18S20s with a set alarm flag will respond to the command, so the master can determine exactly which DS18S20s ha ve experienced an alarm condition. if an alarm condition exists and the t h or t l settings have changed, another temperature c onversion should be done to validate the alarm condition. powering the DS18S20 the DS18S20 can be powered by an external supply on the v dd pin, or it can operate in ?parasite power? mode, which allows the DS18S20 to function without a local external supply. parasite power is very useful for applications that require remote temperat ure sensing or that are very space constrained. figure 1 shows the DS18S20?s parasite-power control circuitry, which ?steals? power from the 1-wire bus via the dq pin when the bus is high. the stolen charge powers the DS18S20 while the bus is high, and some of the charge is stored on the parasite power capacitor (c pp ) to provide power when the bus is low. when the DS18S20 is used in parasite power mode, the v dd pin must be connected to ground. in parasite power mode, the 1-wire bus and c pp can provide sufficient current to the DS18S20 for most operations as long as the specified timing and voltage requirements are met (refer to the dc electrical ch aracteristics and the ac electrical characteristics sections of this data sheet). however, when the DS18S20 is performing te mperature conversions or copying data from the scratchpad memory to eeprom, the operating current can be as high as 1.5ma. this current can cause an unacceptable voltage drop across the weak 1-wire pullup resistor and is more current than can be supplied by c pp . to assure that the DS18S20 has sufficient supply current, it is necessary to provide a strong pullup on the 1-wire bus whenever temperatur e conversions are taking place or data is being copied from the scratchpad to eeprom. this can be accomplished by using a mosfet to pull the bus directly to the rail as shown in figure 4. the 1-wi re bus must be switched to the strong pullup within 10 s (max) after a convert t [44h] or copy scratc hpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (t conv ) or data transfer (t wr = 10ms). no other activity can take place on the 1-wire bus while the pullup is enabled. the DS18S20 can also be powered by the conventiona l method of connecting an external power supply to the v dd pin, as shown in figure 5. the advantage of this method is that the mosfet pullup is not required, and the 1-wire bus is free to carry ot her traffic during the temperature conversion time.
DS18S20 5 of 21 the use of parasite power is not recommended for temperatures above 100 c since the DS18S20 may not be able to sustain communications due to the higher leakage currents that can exist at these temperatures. for applications in which such temperatures are likely, it is strongly recommended that the DS18S20 be powered by an external power supply. in some situations the bus master may not know whether the DS18S20s on the bus are parasite powered or powered by external supplies. the master needs this information to determine if the strong bus pullup should be used during temperature conversions. to get this information, the master can issue a skip rom [cch] command followed by a read power supply [b4h] command followed by a ?read-time slot?. during the read-time slot, parasite powered DS18S20s will pull the bus low, and externally powered DS18S20s will let the bus remain high. if the bus is pulled low, the master knows that it must supply the strong pullup on the 1-wire bus during temperature conversions. supplying the parasite-power ed DS18S20 during temperature conversions figure 4 powering the DS18S20 with an external supply figure 5 64-bit lasered rom code each DS18S20 contains a unique 64-bit co de (see figure 6) stored in rom. the least significant 8 bits of the rom code contain the DS18S20? s 1-wire family code: 10h. the next 48 bits contain a unique serial number. the most significant 8 bits contain a cyclic redundancy check (crc) byte that is calculated from the first 56 bits of the rom code. a detailed explanation of the crc bits is provided in the crc generation section. the 64-bit rom code and associat ed rom function control logic allow the DS18S20 to operate as a 1-wire device using the protocol detailed in the 1-wire bus system section of this datasheet. 64-bit lasered rom code figure 6 8-bit crc 48-bit serial number 8-bit family code (10h) msb msb lsb lsb lsb msb v dd (external supply) DS18S20 gnd v dd dq v pu 4.7k to other 1-wire devices 1-wire bus micro- processor v pu v pu 4.7k 1-wire bus micro- processor DS18S20 gnd v dd dq to other 1-wire devices
DS18S20 6 of 21 memory the DS18S20?s memory is organized as shown in figure 7. the memory consists of an sram scratchpad with nonvola tile eeprom storage for the high a nd low alarm trigger registers (t h and t l ). note that if the DS18S20 alar m function is not used, the t h and t l registers can serve as general-purpose memory. all memory commands are described in detail in the DS18S20 function commands section. byte 0 and byte 1 of the scratchpad contain the lsb and the msb of the temperature register, respectively. these bytes are read-only. bytes 2 and 3 provide access to t h and t l registers. bytes 4 and 5 are reserved for internal use by the device and cannot be overwritten; these byte s will return all 1s when read. bytes 6 and 7 contain the count remain and count per oc registers, which can be used to calculate extended resolution results as explained in the operation ? measuring temperature section. byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (crc) code for bytes 0 through 7 of the scratchpad. the DS18S20 generates this crc using the method described in the crc generation section. data is written to bytes 2 and 3 of the scratchpad using the write scratchpad [4eh] command; the data must be transmitted to the DS18S20 starting with the least significant bit of byte 2. to verify data integrity, the scratchpad can be read (using the read scratchpad [beh] command) after the data is written. when reading the scratchpad, data is transf erred over the 1-wire bus starting with the least significant bit of byte 0. to transfer the t h and t l data from the scratchpad to eeprom, the master must issue the copy scratchpad [48h] command. data in the eeprom registers is retained when the device is powered down; at power-up the eeprom data is reloaded into the corresponding scratchpad locations. data can also be reloaded from eeprom to the scratchpad at any time using the recall e 2 [b8h] command. the master can issue ?read-time slots? (see the 1-wire bus system section) following the recall e 2 command and the DS18S20 will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. DS18S20 memory map figure 7 scratchpad (power-up state) byte 0 temperature lsb (aah) byte 1 temperature msb (00h) eeprom byte 2 t h register or user byte 1* t h register or user byte 1 byte 3 t l register or user byte 2* t l register or user byte 2 byte 4 reserved (ffh) byte 5 reserved (ffh) byte 6 count remain (0ch) byte 7 count per c (10h) byte 8 crc* * power-up state depends on value(s) stored in eeprom (85c)
DS18S20 7 of 21 crc generation crc bytes are provided as part of the DS18S20?s 64-bit rom code and in the 9 th byte of the scratchpad memory. the rom code crc is calculated from the first 56 bits of the rom code and is contained in the most significant byte of the rom. the scratchpad crc is calculated from the data stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. the crcs provide the bus master with a method of data valid ation when data is read from the DS18S20. to verify that data has been read correctly, the bus master must re-calculate the crc from the received data and then compare this value to either the rom code crc (for rom reads) or to the scratchpad crc (for scratchpad reads). if the calculated crc matches the read crc, the data has been received error free. the comparison of crc values and the decision to continue with an operation are determined entirely by the bus master. there is no circuitry inside the DS18S20 that pr events a command sequence from proceeding if the DS18S20 crc (rom or scratchpad) does not match the value generated by the bus master. the equivalent polynomial function of the crc (rom or scratchpad) is: crc = x 8 + x 5 + x 4 + 1 the bus master can re-calculate the crc and compare it to the crc values from the DS18S20 using the polynomial generator shown in figure 8. this circuit c onsists of a shift register and xor gates, and the shift register bits are initialized to 0. starting with th e least significant bit of the rom code or the least significant bit of byte 0 in the sc ratchpad, one bit at a time should shif ted into the shift register. after shifting in the 56 th bit from the rom or the most significant bit of byte 7 from the scratchpad, the polynomial generator will contain the re-calculated crc. next, the 8-bit rom code or scratchpad crc from the DS18S20 must be shifted into the circuit. at this point, if the re-calculated crc was correct, the shift register will contain all 0s. additional information about the da llas 1-wire cyclic redundancy check is available in application note 27: understanding and usi ng cyclic redundancy checks with dallas semiconductor touch memory products. crc generator figure 8 (msb) (lsb) xor xor xor input
DS18S20 8 of 21 1-wire bus system the 1-wire bus system uses a single bus master to control one or more slave devices. the DS18S20 is always a slave. when there is only one slave on the bus, the system is referred to as a ?single-drop? system; the system is ?multidrop? if there are multiple slaves on the bus. all data and commands are transmitted least significant bit first over the 1-wire bus. the following discussion of the 1-wire bus syst em is broken down into three topics: hardware configuration, transaction se quence, and 1-wire signaling (signal types and timing). hardware configuration the 1-wire bus has by definition only a single data lin e. each device (master or slave) interfaces to the data line via an open drain or 3-state port. this allows each device to ?release? the data line when the device is not transmitting data so the bus is available for use by another device. the 1-wire port of the DS18S20 (the dq pin) is open drain with an internal circuit equivalent to that shown in figure 9. the 1-wire bus requires an external pullup resistor of approximately 5k ; thus, the idle state for the 1- wire bus is high. if for any reason a transaction need s to be suspended, the bus must be left in the idle state if the transaction is to resume. infinite recovery time can occur between bits so long as the 1-wire bus is in the inactive (high) state during the recove ry period. if the bus is held low for more than 480 s, all components on the bus will be reset. hardware configuration figure 9 transaction sequence the transaction sequence for acce ssing the DS18S20 is as follows: step 1. initialization step 2. rom command (followed by any required data exchange) step 3. DS18S20 function command (followed by any required data exchange) it is very important to follow this sequence every time the DS18S20 is accessed, as the DS18S20 will not respond if any steps in the sequence are missing or out of order. exceptions to this rule are the search rom [f0h] and alarm search [ech] commands. after issuing either of these rom commands, the master must return to step 1 in the sequence. v pu 4.7k 5a typ. r x t x DS18S20 1-wire port 100 m os fet t x r x r x = receive t x = transmit 1-wire bus dq pin
DS18S20 9 of 21 initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that slave devices (such as the DS18S20) are on the bus and are ready to operate. timing for the reset and presence pulses is detailed in the 1-wire signaling section. rom commands after the bus master has detected a presen ce pulse, it can issue a rom command. these commands operate on the unique 64-bit rom codes of each slave device and allow the master to single out a specific device if many are present on the 1-wire bus. these commands also allow the master to determine how many and what types of devices are present on the bus or if any device has experienced an alarm condition. there are five rom commands, and each co mmand is 8 bits long. the master device must issue an appropriate rom command before issu ing a DS18S20 function command. a flowchart for operation of the rom commands is shown in figure 14. search rom [f0h] when a system is initially powered up, the master mu st identify the rom codes of all slave devices on the bus, which allows the master to determine the number of slaves and their device types. the master learns the rom codes through a process of elimination that requires the master to perform a search rom cycle (i.e., search rom command followed by data exchange) as many times as necessary to identify all of the slave devices. if there is only one slave on the bus, the simpler read rom command (see below) can be used in place of the search rom process. for a detailed explanation of the search rom procedure, refer to the ibutton ? book of standards at www.ibutton.com/ibuttons/standard.pdf . after every search rom cycle, the bus master must return to step 1 (initialization) in the transaction sequence. read rom [33h] this command can only be used when there is one slav e on the bus. it allows the bus master to read the slave?s 64-bit rom code without using the search rom procedure. if this command is used when there is more than one slave present on the bus, a data collision will occur when all the slaves attempt to respond at the same time. match rom [55h] the match rom command followed by a 64-bit rom code sequence allows the bus master to address a specific slave device on a multidrop or single-drop bus. only the slave that exactly matches the 64-bit rom code sequence will respond to th e function command issued by the master; all other slaves on the bus will wait for a reset pulse. skip rom [cch] the master can use this command to address all de vices on the bus simultaneously without sending out any rom code information. for example, the ma ster can make all DS18S20s on the bus perform simultaneous temperature conversions by issuing a skip rom command followed by a convert t [44h] command. note that the read scratchpad [beh] command can follow the skip rom command only if there is a single slave device on the bus. in this case time is saved by allowing the master to read from the slave without sending the device?s 64-bit rom code. a skip rom command followed by a read scratchpad command will cause a data collision on the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously. ibutton is a registered trademark of dallas semiconductor.
DS18S20 10 of 21 alarm search [ech] the operation of this command is identical to the operation of the search rom command except that only slaves with a set alarm flag will respond. this command allows the master device to determine if any DS18S20s experienced an alarm condition during the most recent temperature conversion. after every alarm search cycle (i.e., alarm search command followed by data exchange), the bus master must return to step 1 (initialization) in the transaction sequence. refer to the operation ? alarm signaling section for an explanati on of alarm flag operation. DS18S20 function commands after the bus master has used a rom command to address the DS18S20 with which it wishes to communicate, the master can issue one of the DS18S20 function commands. these commands allow the master to write to and read from the DS18S20?s sc ratchpad memory, initiate te mperature conversions and determine the power supply mode. the DS18S20 func tion commands, which are described below, are summarized in table 4 and illustrated by the flowchart in figure 15. convert t [44h] this command initiates a single te mperature conversion. following th e conversion, the resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18S20 returns to its low-power idle state. if the device is being used in parasite power mode, within 10 s (max) after this command is issued the master must enable a str ong pullup on the 1-wire bus for the duration of the conversion (t conv ) as described in the powering the DS18S20 section. if the DS18S20 is powered by an external supply, the master can issue read- time slots after the convert t command and the DS18S20 will respond by transmitting 0 while the temperature c onversion is in progress and 1 when the conversion is done. in parasite power mode this notification technique cannot be us ed since the bus is pulled high by the strong pullup during the conversion. write scratchpad [4eh] this command allows the master to write 2 bytes of data to the DS18S20?s scratchpad. the first byte is written into the t h register (byte 2 of the scratchpad), and the second byte is written into the t l register (byte 3 of the scratchpad). data must be transmitted least significant bit first. both bytes must be written before the master issues a reset, or the data may be corrupted. read scratchpad [beh] this command allows the master to read the contents of the scratchpad. the data transfer starts with the least significant bit of byte 0 and continues through the scratchpad until the 9 th byte (byte 8 ? crc) is read. the master may issue a reset to terminate reading at any time if only part of the scratchpad data is needed. copy scratchpad [48h] this command copies the cont ents of the scratchpad t h and t l registers (bytes 2 and 3) to eeprom. if the device is being used in pa rasite power mode, within 10 s (max) after this command is issued the master must enable a strong pullup on the 1-wi re bus for at least 10ms as described in the powering the DS18S20 section. recall e 2 [b8h] this command recalls the alarm trigger values (t h and t l ) from eeprom and places the data in bytes 2 and 3, respectively, in the scratchpad memory. the master device can issue read-time slots following the recall e 2 command and the DS18S20 will indi cate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. the recall operation happens automatically at power- up, so valid data is available in the scratchpad as soon as power is applied to the device.
DS18S20 11 of 21 read power supply [b4h] the master device issues this command followed by a read-time slot to determine if any DS18S20s on the bus are using parasite power. during the read-time slot, parasite powered DS18S20s will pull the bus low, and externally powered DS18S20s will let the bus remain high. refer to the powering the DS18S20 section for usage information for this command. DS18S20 function command set table 4 command description protocol 1-wire bus activity after command is issued notes temperature conversion commands convert t initiates temperature conversion. 44h DS18S20 transmits conversion status to master (not applicable for parasite-powered DS18S20s). 1 memory commands read scratchpad reads the entire scratchpad including the crc byte. beh DS18S20 transmits up to 9 data bytes to master. 2 write scratchpad writes data into scratchpad bytes 2 and 3 (t h and t l ). 4eh master transmits 2 data bytes to DS18S20. 3 copy scratchpad copies t h and t l data from the scratchpad to eeprom. 48h none 1 recall e 2 recalls t h and t l data from eeprom to the scratchpad. b8h DS18S20 transmits recall status to master. read power supply signals DS18S20 power supply mode to the master. b4h DS18S20 transmits supply status to master. notes: 1) for parasite-powered DS18S20s, the master must enable a strong pullup on the 1-wire bus during temperature conversions and copies from the scra tchpad to eeprom. no other bus activity may take place during this time. 2) the master can interrupt the transmission of data at any time by issuing a reset. 3) both bytes must be written before a reset is issued.
DS18S20 12 of 21 1-wire signaling the DS18S20 uses a strict 1- wire communication protocol to insure data integrity. several signal types are defined by this protocol: reset pulse, presence pul se, write 0, write 1, read 0, and read 1. all of these signals, with the exception of the presence pulse, are initiated by the bus master. initialization procedure: reset and presence pulses all communication with the DS18S20 begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the DS18S20. this is illustrated in figure 10. when the DS18S20 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. during the initialization sequence the bus master transmits (t x ) the reset pulse by pulling the 1-wire bus low for a minimum of 480 s. the bus master then releases the bus and goes into receive mode (r x ). when the bus is released, the 5k pullup resistor pu lls the 1-wire bus high. when the DS18S20 detects this rising edge, it waits 15 s to 60 s and then transmits a presence pulse by pulling the 1-wire bus low for 60 s to 240 s. initialization timing figure 10 read/write time slots the bus master writes data to the DS18S20 during write time slots and reads data from the DS18S20 during read-time slots. one bit of data is transmitted over the 1-wire bus per time slot. write time slots there are two types of write time slots: ?write 1? time slots and ?write 0? time slots. the bus master uses a write 1 time slot to write a logic 1 to the DS18S20 and a write 0 time slot to write a logic 0 to the DS18S20. all write time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual write slots. both types of write time slots are initiated by the master pulling the 1-wire bus low (see figure 11). to generate a write 1 time slot, after pulling the 1-wire bus low, the bus master must release the 1-wire bus within 15 s. when the bus is released, the 5k pullup resistor will pull the bus high. to generate a write 0 time slot, after pulling the 1-wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60 s). the DS18S20 samples the 1-wire bus during a window that lasts from 15 s to 60 s after the master initiates the write time slot. if the bus is high during the sampling window, a 1 is written to the DS18S20. if the line is low, a 0 is written to the DS18S20. line type legend bus master pulling low DS18S20 pulling low resistor p ullu p v pu gnd 1-wire bus 480 s minimum 480 s minimum DS18S20 t x presence pulse 60-240 s master t x reset pulse master r x DS18S20 waits 15-60 s
DS18S20 13 of 21 read-time slots the DS18S20 can only transmit data to the master when the master issues read-time slots. therefore, the master must generate read-time slots immediately after issuing a read scratchpad [beh] or read power supply [b4h] command, so that the DS18S20 can provide the requested data. in addition, the master can generate read-time slots after i ssuing convert t [44h] or recall e 2 [b8h] commands to find out the status of the operation as explained in the DS18S20 function command section. all read-time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between slots. a read-time slot is initiated by the master device pulling the 1-wire bus low for a minimum of 1 s and then releasing the bus (see figure 11). after the master initiates the read-time slot, the DS18S20 will begin transmitting a 1 or 0 on bus. the DS18S20 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. when transmitting a 0, the DS18S20 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. output data from the DS18S20 is valid for 15 s after the falling edge that initiated the read-time slot. therefore, the master must release the bus and then sample the bus state within 15 s from the start of the slot. figure 12 illustrates that the sum of t init , t rc , and t sample must be less than 15 s for a read-time slot. figure 13 shows that system timing margin is maximized by keeping t init and t rc as short as possible and by locating the master sample time during read-time slots towards the end of the 15 s period. read/write time slot timing diagram figure 11 45 s 15 s v pu gnd 1-wire bus 60 s < t x ?0? < 120 s 1 s < t rec < DS18S20 samples min typ ma x 15 s 30 s > 1 s master write ?0? slot master write ?1? slot v pu gnd 1-wire bus 15 s master read ?0? slot master read ?1? slot master samples master samples start of slot start of slot > 1 s 1 s < t rec < 15 s 15 s 30 s 15 s DS18S20 samples min typ ma x > 1 s line type legend bus master pulling low DS18S20 pulling low resistor pullup
DS18S20 14 of 21 detailed master read 1 timing figure 12 recommended master read 1 timing figure 13 v pu gnd 1-wire bus 15 s v ih of master t rc t int > 1 s master samples line type legend bus master pulling low resistor pullup v pu gnd 1-wire bus 15 s v ih of master t rc = small t int = small master samples
DS18S20 15 of 21 rom commands flow chart figure 14 cch skip rom command master t x reset pulse DS18S20 t x presence pulse master t x rom command 33h read rom command 55h match rom command f0h search rom command ech alarm search command master t x bit 0 DS18S20 t x bit 0 DS18S20 t x bit 0 master t x bit 0 bit 0 mat c h? master t x bit 1 bit 1 match? bit 63 mat c h? master t x bit 63 n y yyy y nn n n n n n y y y DS18S20 t x bit 1 DS18S20 t x bit 1 master t x bit 1 DS18S20 t x bit 63 DS18S20 t x bit 63 master t x bit 63 bit 0 mat c h? bit 1 match? bit 63 match? n n n y y y DS18S20 t x family code 1 byte DS18S20 t x serial number 6 bytes DS18S20 t x crc byte DS18S20 t x bit 0 DS18S20 t x bit 0 master t x bit 0 n y device(s) with alarm flag set? initialization sequence master t x function command (figure 15)
DS18S20 16 of 21 DS18S20 function commands flow chart figure 15 master t x function command y n 44h convert temperature ? parasite power ? n y DS18S20 begins conversion device converting temperature ? n y master r x ?0s? master r x ?1s? master enables strong pullup on dq DS18S20 converts temperature master disables strong pullup y n 48h copy scratchpad ? parasite power ? n y master enables strong pull-up on dq data copied from scratchpad to eeprom master disables strong pullup master r x ?0s? copy in progress ? y master r x ?1s? n return to initialization sequence (figure 14) for next transaction b4h read power supply ? y n parasite powered ? n master r x ?1s? master r x ?0s? y master t x t h byte to scratchpad y n 4eh write scratchpad ? master t x t l byte to scratchpad y n y beh read scratchpad ? have 8 bytes been read ? n master t x reset ? master r x data byte from scratchpad n y master r x scratchpad crc byte master r x ?1s? y n b8h recall e 2 ? master begins data recall from e 2 prom device busy recalling data ? n y master r x ?0s?
DS18S20 17 of 21 DS18S20 operation example 1 in this example there are multiple DS18S20s on the bus and they are using parasite power. the bus master initiates a temperature c onversion in a specific DS18S20 a nd then reads its scratchpad and recalculates the crc to verify the data. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence DS18S20s respond with presence pulse. tx 55h master issues match rom command. tx 64-bit rom code master sends DS18S20 rom code. tx 44h master issues convert t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence DS18S20s respond with presence pulse. tx 55h master issues match rom command. tx 64-bit rom code master sends DS18S20 rom code. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. DS18S20 operation example 2 in this example there is only one DS18S20 on the bus a nd it is using parasite power. the master writes to the t h and t l registers in the DS18S20 scratchpad and then reads the scratchpad and recalculates the crc to verify the data. the master then copies the scratchpad contents to eeprom. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence DS18S20 responds with presence pulse. tx cch master issues skip rom command. tx 4eh master issues write scratchpad command. tx 2 data bytes master sends two data bytes to scratchpad (t h and t l ) tx reset master issues reset pulse. rx presence DS18S20 responds with presence pulse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. tx reset master issues reset pulse. rx presence DS18S20 responds with presence pulse. tx cch master issues skip rom command. tx 48h master issues copy scratchpad command. tx dq line held high by strong pullup master applies strong pullup to dq for at least 10ms while copy operation is in progress.
DS18S20 18 of 21 DS18S20 operation example 3 in this example there is only one DS18S20 on the bus and it is using parasite power. the bus master initiates a temperature conversion then reads the ds 18s20 scratchpad and calcula tes a higher resolution result using the data from the temperature, count remain and count per c registers. master mode data (lsb first) comments tx reset master issues reset pulse. tr presence DS18S20 responds with presence pulse. tx cch master issues skip rom command. tx 44h master issues convert t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence DS18S20 responds with presence pulse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. the master also calculates the temp_read value and stores the contents of the count remain and count per c registers. tx reset master issues reset pulse. rx presence DS18S20 responds with presence pulse. - - cpu calculates extended resolution temperature using the equation in the operation ? measuring temperature section of this datasheet.
DS18S20 19 of 21 absolute maximum ratings* voltage on any pin relativ e to ground -0.5v to +6.0v operating temperature range -55 c to +125 c storage temperature range -55 c to +125 c solder temperature see ipc/jedec j-std-020a reflow oven temperature +220c *these are stress ratings only and functional operati on of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (-55c to +125c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units notes supply voltage v dd local power +3.0 +5.5 v 1 parasite power +3.0 +5.5 pullup supply voltage v pu local power +3.0 v dd v 1, 2 -10c to +85c 0.5 c 3 thermometer error t err -55c to +125c 2 input logic low v il -0.3 +0.8 v 1, 4, 5 local power +2.2 input logic high v ih parasite power +3.0 the lower of 5.5 or v dd + 0.3 v 1, 6 sink current i l v i/o =0.4v 4.0 ma 1 standby current i dds 750 1000 na 7, 8 active current i dd v dd =5v 1 1.5 ma 9 dq input current i dq 5a10 drift 0.2 c 11 notes: 1) all voltages are referenced to ground. 2) the pullup supply voltage specification assumes that the pullup device is ideal, and therefore the high level of the pullup is equal to v pu . in order to meet the v ih spec of the DS18S20, the actual supply rail for the strong pullup transistor must include margin for the voltage drop across the transistor when it is turned on; thus: v pu_actual = v pu_ideal + v transistor . 3) see typical performance curve in figure 16 4) logic low voltages are specified at a sink current of 4ma. 5) to guarantee a presence pulse under low voltage parasite power conditions, v ilmax may have to be reduced to as low as 0.5v. 6) logic high voltages are specified at a source current of 1ma. 7) standby current specified up to 70 c. standby current typically is 3 a at 125 c. 8) to minimize i dds , dq should be within the following ranges: gnd dq gnd + 0.3v or v dd ? 0.3v dq v dd . 9) active current refers to supply current during active temperature convers ions or eeprom writes. 10) dq line is high (?hi-z? state). 11) drift data is based on a 1000 hour stress test at 125c with v dd = 5.5v.
DS18S20 20 of 21 ac electrical characteristics: nv memory (-55c to +100c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units nv write cycle time t wr 210 ms eeprom writes n eewr -55c to +55c 50k writes eeprom data retention t eedr -55c to +55c 10 years ac electrical characteristics (-55c to +125c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units notes temperature conversion time t conv 750 ms 1 time to strong pullup on t spon start convert t command issued 10 s time slot t slot 60 120 s 1 recovery time t rec 1s1 write 0 low time r low0 60 120 s 1 write 1 low time t low1 115s1 read data valid t rdv 15 s 1 reset time high t rsth 480 s 1 reset time low t rstl 480 s 1, 2 presence detect high t pdhigh 15 60 s 1 presence detect low t pdlow 60 240 s 1 capacitance c in/out 25 pf notes: 1) refer to timing diagrams in figure 17. 2) under parasite power, if t rstl > 960 s, a power on reset may occur. typical performance curve figure 16 DS18S20 typical error curve -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 10203040506070 temperature (c) mean error +3s error -3s error
DS18S20 21 of 21 timing diagrams figure 17

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